Is Intel about to drown the cloud in data, or show how to make it shine?

Kevin Fogarty, freelance IT journalist
Kevin Fogarty, freelance IT journalist

Kevin Fogarty is writer, editor, columnist and tech analyst with over 20 years’ experience covering IT, mobile and business computing, science and healthcare technologies. He has worked with most of the major publishing brands brands, including ITWorld,, Ziff Davis and TechTarget, in roles ranging from content creation to content management and strategy. Drawing on this long term participation in the industry, Fogarty has developed in-depth understanding of the key IT trends and technologies that have shaped the contemporary tech landscape. In the article below, he demonstrates this background and considerable analytical skill, outlining Intel efforts to produce chips that are purpose-built for cloud computing. We are pleased to feature Fogarty’s first contribution to InsightaaS, and look forward to upcoming tales from the tech edge!

The launch of Intel Corp.’s newest high-performance server chip on Sept. 8 was accompanied by all the usual extras: partner-product announcements, arcane discussion of advanced microarchitectures and detailed but imprecise roadmaps of future development.

In addition to bragging about the power and sophistication of the new chip, however, Intel went into some detail about why the new Xeon E5 2600 v3 — with three times the performance, six times the data throughput and half the latency of earlier editions — should be considered not a microprocessor, but a cloud-computing product.

Intel described the new chip as having been designed specifically — “optimized for cloud computing, or “agile datacenters” — but not just because it might make a good choice to power servers in heavily virtualized data centres.

The new chip is designed to become an integral part of the cloud as it presents its on-board resources to be virtualized, managed and reassigned as needed. Rather than function as a single processor in a single server in a single rack of a single datacenter, E5 Haswell-EP chips are designed to behave as if each of as many as 18 processing cores is a separate computer and as if the processor itself is a cluster of servers.

“The digital services economy imposes new requirements on the data center, requirements for automated, dynamic and scalable service delivery,” according to a published statement from Diane Bryant, SVP and GM of Intel’s Data Center Group. “Our new Intel processors deliver unmatched performance, energy efficiency and security, as well as provide visibility into the hardware resources required to enable software defined infrastructure.” Slides from Bryant’s Sept. 8 presentation at the Intel Developers’ Forum are available here; a video of the event is here.

The functional idea is to apply to processors the same benefits in capacity utilization, workload optimization and dynamic use of computing resources that made first server virtualization and then

cloud-computing infrastructure software a hit within corporate data centres.

The strategic idea is to put Intel at the heart of the movement toward Software Defined Infrastructure (SDI), a conceptual model of computing in which layers of virtualization give administrators fine-grained control over many systems and networks simultaneously from a single console.

Intel has been promoting its own SDI concept called “Re-Architecting the Datacenter” since 2013, and framed its Xeon E5 2600 v2 — released in September of 2013 — as an advancement in the delivery of flexible, computing-services-oriented computing.

“Offering new cloud-based services requires an infrastructure that is versatile enough to support diverse workloads and is flexible enough to respond to changes in resource demand across servers, storage and network,” according to a statement issued at the time from Diane Bryant.

That flexibility was more aspiration than virtualization, however. Intel partners were supposed to build the actual servers. The actual flexibility was supposed to come from Intel’s Open Network Platform (ONP), a server-reference design that included support for open-stack SDI projects including OpenStack cloud software,  OpenvSwitch virtual network switching and the OpenDaylight software-defined networking (SDN) development project.

ONP and the technologies that comprised it are still around, but Intel has a much better story to tell about a chip that is inherently oriented toward the cloud than it did with Xeon E5 v2 during 2013.

The Xeon E5 2600 v3 was designed with sensors built into the chip itself in order that it need not rely on those outside, and included a variety of fine-grained controls that may currently be too fine-grained to be useful to most organizations, but which do address the software-configurability and resource-distribution demands Intel describes.

Fast-forward a year, and v3 of Intel’s Xeon E5 appears to have some of the flexibility built into the processor rather than into the announcement.

Manageability comes via Intel Node Manager 3.0, firmware that, among other things, collects telemetry from sensors built into the die and makes real-time data on utilization levels, heat and power usage available to applications able to read it.

Building sensors into the chip itself — rather than relying on heat sensors built into the motherboard, for example — represents a fundamental change in processor design by providing a standard set of telemetry functions that can be expected from the processor, a standard data set and standard way to communicate that data to systems or network-management applications.

Intel Node Manager provides information on the chip’s performance; a “fully integrated voltage regulator” (FIVR) built into the die itself provides the control.

Every system has voltage regulators to control the flow of power to the processor. Most are outside the chip, however, and provide shallow degrees of control by allowing power to be raised or lowered to the entire chip.

Intel built voltage regulation into the chip and made the controls themselves far more granular by applying FIVR ability to each core individually, allowing for change in the voltage level and clock speed of each processing core individually.

The memory cache management function also built into the firmware is able to identify which thread is being processed by which core, which could help optimize application performance by identifying individual threads that are causing problems.

It can also, according to Bryant, identify badly behaved virtual machines known as “noisy neighbours” that use more than their share of system resources, starving others on the same machine.

The same function that allows monitoring of cache usage by thread also allows a “cluster-on-die” capability that allows administrators to change the way a subset of a processor’s cores use memory to give more power and priority to those handling resource-intensive processes or less to those with less stressful tasks.

FIVR also provides a manageable link to power on the “uncore” — the portion of the chip that is separate from the core but which handles data I/O, non-core processors that handle arithmetic and floating-point calculations, sections that house the on-chip memory, memory controllers, the QuickPath Interconnect (QPI) that moves data around the chip itself, and the “snoop agent” that keeps track of what portions of memory each core is using to keep them from conflicting.

Dropping the voltage on a core that is not being fully utilized by an existing workload — and relying on extra power as needed from the Turbo Boost function common to many Intel chips — can make a monster processor more power efficient, without necessarily giving up performance.

Performance controls on the Xeon E5 get more granular still, however.  Software-based voltage regulation controls allowed Intel to add a feature called Per Core P-States (PCPS) that allows firmware controls to change the frequency and voltage of each core to maximize performance or minimize power use.

It also added a feature called Uncore Voltage/Frequency Scaling (UFS), which allows administrators to change the power levels of “uncore” segments including QPI, the high-speed transport that moves data from one region of the chip to another, the I/O controller that can increase or decrease bandwidth for processes based on priority and the on-die memory controller that decides which portions of the processor have access to the processor’s richest resource, and how much of it each should have.

Intel has yet to demonstrate that all, or even most, of these functions are workable and accessible in ways that would make practical performance monitoring and control of the new Xeon possible.

It might take even longer to demonstrate it would be practical or desirable for whole organizations — or even managers of individual applications — to use those functions to effectively tune the performance of applications and data spread across dozens or hundreds of servers.

Intel already has believers, however. The company announced on Sept. 8 that it would ship 27 different configurations of Xeon E5 chips.

Along with the list of Xeon E5 configurations it will ship commercially, Intel announced it had accepted orders for 20 versions of the chip customized to the specific workloads or requirements of particular customers. For Microsoft it added additional cores, faster encryption and faster compression to chips it is building for “the unique requirements of our large cloud-scale data centers,” according to a customer-testimonial accompanying Intel’s announcement from Kushagra Vaid, GM of Cloud Server Engineering at Microsoft Corp., who also appeared with Bryant on stage at IDF.

Of the other customer testimonials, only one from Baidu — China’s homegrown version of Google — mentioned performance-management rather than performance, and that only in the context of minimizing the use of power and heat generated in hyperscale data centres.



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